1. Technical Field
The present invention is directed generally toward a method and apparatus for enhancing the correction power of reverse order error correction codes.
2. Description of the Related Art
Read channel integrated circuits for magnetic storage often contain significant digital signal processing and error correction logic to reliably reconstruct the original data stored on the media. Simplified block diagrams for this signal processing and error correction functions are given in FIGS. 1A and 1B for a typical implementation of the encode and decode side of the process. Particularly, FIG. 1A illustrates a typical implementation of an encode process. Data is received by error correction code (ECC) encoder 105. ECC encoder 105 generates check bits, which are typically concatenated to the end the sector. Thus, a predetermined number of bits of error correction code are computed for every unit of data being stored. When data is retrieved, the ECC syndromes are computed to determine if any of the data bits have been corrupted. Traditionally, the ECC encoder resides in the data controller chip.
Constraint encoder 110 receives the ECC encoded data from the ECC encoder. Constraint encoding is an encoding method commonly used on magnetic disks. A run length limited (RLL) encoder is an example of a constraint encoder. The actual number of bits recorded on the disk is greater than the data bits. The data is encoded to limit the length of certain patterns in the data for timing recovery and/or error suppression reasons. As electronics improve, fewer extra bits are inserted, and the ratio of data bits to recorded bits becomes greater. The xe2x80x9crun lengthxe2x80x9d is the number of consecutive zeros before a one bit is recorded. For example, RLL 1,7 means there must be at least one zero bit between every one bit, and the 7 means a maximum of eight time periods between flux transitions. Constraint 110 and the remainder of the encode process typically resides in the read channel chip. The constraint encoded data is received by post processing encoder 115, which further encodes data for write logic and driver 120. The write logic and driver outputs analog data to the storage device.
Turning to FIG. 1B, a typical decode process is depicted. Analog front end (AFE) 150 receives analog data in from a storage device and analog-to-digital converter (ADC) 155 converts the data to digital. Finite impulse response (FIR) 160 filters the data. Viterbi detector 165 is a maximum likelihood detector that computes the most likely data sequence. Post processor 170 performs processing on the Viterbi data. Constraint decoder 175 removes the constraint code. These elements of the decode process traditionally reside in the read channel chip. ECC decoder 180 decodes the error correction code and outputs corrected data. The ECC decoder traditionally resides in the data controller chip.
Analog Front End accepts analog signals from the pre-amp and filters it before the ADC digitizes it. The FIR (Finite Impulse Response) Filter conditions the digitized signal by digitally filtering it and attempts to match a xe2x80x9ctargetxe2x80x9d.
As silicon processing improved over time allowing increased integration of functions on the same chip and as the error propagation properties of the constraint decoder have worsened, the idea of reverse order ECC has emerged. The basic idea of reverse order ECC, sometimes called reverse ECC, is to switch the order of the constraint and ECC encoding/decoding. Switching the order of the constraint decoder and the ECC decoder allows the full strength of the ECC to be utilized without the diluting effect of the constraint decoder""s error multiplication properties. This change in structure for reverse ECC is shown in FIGS. 2A and 2B.
Particularly, FIG. 2A illustrates a typical reverse ECC encode process. In the encode process of FIG. 2A, constraint encoder 205 and ECC encoder 210 are reversed. The ECC bits which are typically concatenated at the end of the data sector, may not conform to the constraint requirements and may need to pass through a separate and different constraint encoder. Post processing encoder 215 may not be beneficial and may be removed from the process. Turning to FIG. 2B, a typical reverse ECC decode process is depicted. In the decode process of FIG. 2B, ECC decoder 275 and constraint decoder 280 are reversed. Thus, the full strength of ECC decoder 275 may be realized without errors being multiplied by constraint decoder 280.
A Viterbi detector finds the most likely binary sequence given a stream of digitized data in a least mean square error sense. A Viterbi detector is used when inter-symbol interference is involved in the signal, that is, when signals overlap each other.
If the encoding of a constraint code spans over multiple ECC symbols, error propagation can occur. This is because an error might be limited to a short span before constraint code decoding but fans out to additional bits when decoded. An increase in errors, due to errors being multiplied by a constraint decoder, results in a higher sector retry/failure rate. A retry due to uncorrectable data is time consuming. Therefore, it would be advantageous to provide improved correction power for ECC decoding during a reverse ECC decode process to avoid an increase in the number of repeated retrievals due to uncorrectable data.
The present invention takes advantage of information available from a post processor. This information is a list of highly probable error event patterns and locations found by employing a list Viterbi or a set of matched filters on Viterbi data This list of possible errors can be used by the ECC decoder in an iterative process whenever the correction power of the ECC is exceeded. If the ECC decoder cannot correct the data on its first unassisted try, an iterative process is employed which, in essence, modifies the data with potential errors identified from the list created by the post processor and tries the correction process over again. An algorithm may be employed to try each error singly or in combination with other errors. This iterative process continues until a correctable indication is given by the ECC algorithm. The data is then corrected with the ECC results and the corresponding error list.